Semiconductor manufacturers are continuously striving to produce faster and more complex integrated circuits. One way to achieve this is to reduce the dimensions of the semiconductor circuits, thereby decreasing the gate (transistor) delay. However, as the dimensions of the circuits are reduced, the physical properties of the materials making up the circuits become increasingly important. In particular, as the size of the conducting interconnects contained in the circuit, and more particularly their width, decreases, the electrical resistance of the interconnect is proportionately increased. This causes an increased interconnect time delay. Until recently, aluminium had been traditionally used to manufacture these interconnects. However, in order to combat the problems associated with the reduction in the circuit dimensions, semiconductor manufacturers have decided that copper provides better material characteristics than aluminium for use in interconnects because of its lower bulk resistivity, higher heat conductivity and higher melting point, which results in improved speed and reliability performance. In addition, copper also has lower rate of grain boundary diffusion, and therefore higher electromigration resistance.
In order to provide conducting interconnects between and within layers of a semiconductor device, a method sometimes termed a “damascene” process has been developed. This process first involves deposition of a dielectric layer, lithography and then etching of the dielectric layer to form vias and/or trenches in the layer. A barrier layer such as Ta is first deposited (typically via physical vapour deposition or atomic layer deposition) in the trenches followed by a thin seed layer. The seed layer may also be deposited by physical vapour deposition, chemical vapour deposition or atomic layer deposition. The seed layer is a conducting layer that allows electrodeposition to occur and typically comprises copper or a copper alloy such as CuAl. The substrate is then subjected to an electroplating (electrodeposition) process in order to fill the recessed trenches and vias with copper. The electroplating may continue until all of the recessed features are filled, which may involve continuing with electrodeposition until an overburden is formed (a layer on the surface of the substrate typically less than 2 microns thick). The overburden may be removed using a process such as chemical mechanical polishing.
It is known to use a pre-rinse step after the deposition of a seed layer and before electrodeposition of the copper, which is simply to clean the surface of the substrate and to remove contaminants, which may result in defect formation. Generally, the dielectric substrate is pre-rinsed with deionised or distilled water. Such a process is disclosed in U.S. Pat. No. 6,491,806 B1.
Researchers have found that, for increasingly narrow vias (having a diameter less than 200 nm), there is an increased likelihood of defect formation in the copper interconnects when they are filled during electrodeposition. This is due to the way the copper is deposited onto the surfaces in and around recessed features during electrodeposition. During ‘normal’ electrodeposition (in which no organic additives are present in the electrolyte solution) onto a seeded dielectric substrate, it has been found a metal will deposit more quickly around the top edges of a via or trench compared to the bottom. The increased amount of copper deposition on the sides around the rim of a recessed feature can lead to a cavity forming in the copper as the electrodeposition progresses. This increased deposition around the rim of a recessed feature is due to two factors: (i) the transport of copper ions to the top of recessed feature is greater than to the bottom of recessed feature, largely due to diffusion, and (ii) there is higher electric field around the rim due to its closer proximity to the anode.
Alternatively, the recessed feature may be filled ‘conformally’, i.e. the metal deposition follows the conformation of recessed structure. This can lead to a vertical thin seam forming at the centre of recessed structure, which is undesirable. This seam can interfere with copper recrystallization and may trap electrolyte. It has been found that an excess of a suppressor in the electrolyte solution seems to promote this conformal filling.
With large recessed features (width>1 micron) ‘normal’ and ‘conformal’ deposition do not tend to result in defect formation, so the nature of the deposition was not so much of a concern for the filling these larger recessed features.
The most desirable way in which a narrow recessed feature is filled is in a ‘bottom-up’ or ‘superconformal’ manner, i.e. where the conductive material is deposited significantly faster at the bottom of the feature than on its side walls. Recent advances have provided deposition processes in which the filling of vias is in a superconformal manner. This generally involves using a combination of additives in the electrolyte solution, such as a organic polyether “suppressor” additive (such as PEG or copolymers of PEO/PPO), in combination with a smaller organic thiolate molecule “accelerator” additive (such as SPS).
The adsorption and incorporation behaviour of the adsorbed suppressor and accelerator molecule are unique. The thiolate accelerator, for instance, tends to float at the surface undergoing deposition while the suppressor may be displaced or incorporated into the electrodeposited copper. The difference in adsorption causes the floating thiolates to crowd together in the bottom of recessed structures. As a result of thiolate crowding at the bottom of recessed structures, the local deposition rate is increased (or accelerated) and bottom-up or superconformal filling is realized.
A “suppressor” is defined as a species that can adsorb on to the surface of a conductive material (for example a metal such as copper or an alloy thereof) and decreases the rate of electrodeposition of a metal (for example copper or an alloy thereof) on to the surface (on which the suppressor is adsorbed) compared to electrodeposition under the same conditions but in which no suppressor is present. Typical examples of suppressor polyethers are polyethylene glycol (PEG), polypropylene glycol (PPG) and block copolymers of polyethylene oxide and polypropylene oxide. Molecular weights of the suppressors may range from 500 to 20000 g/mol.
An “accelerator” (which is sometimes referred to in the art as a brightener or an anti-suppressor) is defined as a species that can adsorb on to the surface of a conductive material (for example a metal such as copper or an alloy thereof) and increases the rate of electrodeposition of a metal (for example copper or an alloy thereof) on to the surface (on which the accelerator is adsorbed) compared to electrodeposition under the same conditions but in which no accelerator is present. Typically, accelerators are sulphur-containing thiolates such as SPS (bis(3-sulfopropyl)-disodium-sulfoxide).
Accelerators and suppressors are known to those skilled in the art.
The present inventors have found that in electrodeposition processes in which superconformal filling occurs (e.g. using electrolytes containing accelerators and suppressors), there is still usually an initial stage where deposition onto the seed layer is conformal. There is a desire to reduce or eliminate this initial conformal filling since excessive conformal deposition results in voids.